The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, in FinFET fabrication processes, it has become challenging to continually increase fin density and decrease fin geometry while providing high circuit performance. On the one hand, the market demands higher device integration, which means more FinFETs (hence, more fins) per unit wafer area. This leads to very narrow fin-to-fin space between adjacent FinFETs. On the other hand, the narrow fin-to-fin space limits the growth of S/D epitaxial features in order to prevent accidental shorting of the S/D features. When S/D epitaxial features become smaller, there is less landing area for S/D contacts, thus leading to increased S/D contact resistance. Furthermore, narrow fin-to-fin space also increases coupling capacitance between adjacent gate structures. Both the increased S/D contact resistance and the increased coupling capacitance adversely impact the device performance. Accordingly, improvements in these areas of FinFET fabrication are desirable.